Why do two Avalon_MM_Pipeline Bridges respond differently to READ

The 'lock up' is probably caused by the addressed slave not responding correctly to all the bus cycle signals.

You also want to make all your slaves 32bit (eg by returning 0 for any unwanted high bits) rather than having any 8 or 16 bit slaves.

If the widths mismatch logic is added to generate multiple cycles on the slave side - some of which are likely to have no asserted byte enables.