Why do two Avalon_MM_Pipeline Bridges respond differently to READ

Thank you !!! One of the slaves is on a slower clock so it probably adds clock crossing logic for all.

Now, here is another twist, I am using generic SW drivers: "IOWR_32DIRECT, IORD_32DIRECT" for my verification, they work fine for slaves on the "good" bus but lock up on the troubled bus. You would think that they would for both, slow and fast busses. Again, the HW simulation works fine...

One more question: where can I find info. on QSYS "under the hood works"? I would like to understand what there translators and limiters, etc. are.

Thanks again.

Shvitzer