--- Quote Start ---
Hi vaka,
which Hardware you are using? If there is an ethernet example for it then the best way will be to start with that.
If you have an ethernet connection running the MAC and PHY are properly initialized, you can read the register settings.
for the TSE Registers
ulRegValue = IORD_32DIRECT( TSE_MAC_BASE, REG_OFFSET );
for the PHY Registers via MDIO Interface
ulRegValue = IORD_32DIRECT( TSE_MAC_BASE + 0x200, REG_OFFSET );
If you will use the Interniche TCP/IP stack you can look at the function tse_mac_init(int iface) in ins_tse_mac.c for initialization of MAC and PHY.
(in \altera\14.1\ip\altera\ethernet\altera_eth_tse\src\software\lib\UCOSII\src\iniche\)
Jens
--- Quote End ---
Hi Jens,
I am using Stratix V SI transceiver development kit board with instantiated TSE without Qsys and without Nios. I will do raw Ethernet, so no need for TCP/IP. I have simulated the behaviour of the handwritten logic above MAC and it works fine. So, the Avalon ST interface is finished, however I am having problems receiving data from the PC and I assume the it is some kind of problem with the initialization. Is it mandatory to do the initialization, what happens if I don't configure the registers? I am sending broadcast frames from the PC, so those should pass anyway no matter the MAC address of my FPGA. What else could be going wrong with the MAC and PHY that stops me from receiving anything after the MAC?
Honored Contributor
