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Altera_Forum
Honored Contributor
Honored ContributorWhat's the difference between an Avalon MM Master and an Avalon MM Slave
I need to design an Avalon MM IP component that allows software running on the HPS of a Cyclone V FPGA to access an external comms chip and an SRAM chip. The comms chip has a memory mapped register s...
Altera_ForumHonored Contributor
Honored ContributorThe ghrd for the Altera Cyclone V has two JTAG to Avalon Master Bridges, hps_only_master and fpga_only_master. As far as I can see these allow you to test the board using system console via the JTAG interface for board bring-up and testing - is this correct? If so, our production board can't include this function as it runs a safety critical application.
My question is, when I've implemented my custom avalon memory-mapped interface component, how do I connect it in Qsys to allow the HPS to access it? What mechanism does the HPS use to communicate with slaves if we don't have a JTAG to Avalon Master Bridge?
