What's the burst length of SDRAM in Nios II?

Honored Contributor

21 years ago

TO Clancy:

Thank you for your quick reply.

In the "Pointer++" case, I use SRAM as my data Memory & Program Memory while I let

the "Pointer" point to somewhere in SDRAM. The data read from SDRAM is given to a variable which

I think resides in SRAM (since the SRAM is my data & program memory).

In my project, I'll use 2 SDRAMs and the bulk data transfering is between FIFO and the SDRAMs or

between the 2 SDRAMs,the read/write/read/write case will not be done on the same SDRAM at the same

time. May be this method will achieve a good bandwidth.

By the way, can you give some advice of the memory assignments in my project? I want to use

2 SDRAMs to store images and SRAM as the data & program memory; bulk data transfering is carried out

among on-chip FIFOs and SDRAMs through DMA(s). In this way, SDRAMs are only used as storage bin, the

frequent instructions and data accessing of the CPU is carried out between CPU and SRAM without interfering

the bulk data transfering. But one thing pains me is that the DMA of NiosII will not work properly, I dont know

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