What's the burst length of SDRAM in Nios II?

You're Welcome RM!

I've been struggling to port proven code from a 55MHz Motorola Coldfire to a 75MHz NiosI/II for months. It's somewhere between 30% and 50% of the performance on the NiosI/II.

I believe the lack of a single instruction to read/write *and* increment/decrement the address all in one clock is partially to blame. On Coldfire the *pointer++ can map to something like LDW g1, (addr)+.

Super fast sram or even cache is not going to help when you need an instruction to do the load or store and another (at least) to increment.

I see in several of the .s files that typically there is a LDBIO r4, (r11) followed by a ADDI r11, 1 to increment.

Need to add postincremental adressing i.e. LDBIO r4, (r11)+. Pre/Postdecrementing is nice too LDBIO r4, -(r11).

Hopefully this is available at least if I code by hand.

I was wondering if I could do something with loops I know I can unroll.

for(i=0 ; i<max_i ; i+=4)

{

LDW r4, 0(r11)

//do stuff with r4

LDW r4, 1(r11)

//do stuff with r4

LDW r4, 2(r11)

// ditto

LDW r4, 3(r11)

}

Clumsy though. Any clever ideas?

Ken