Forum Discussion
Altera_Forum
Honored Contributor
21 years agoTo Kenland & Clancy:
Thank you! I have got the two ideas from the Modelsim Simulation Waveform: *The burst length of @ltera's SDRAM Controller is 1(just like what Clancy mentioned), maybe we cannot modify it while we can do such thing to DDR SDRAM Controller. *The SDRAM can realize almost one work per clock when the controller sends "Read" commands consecutively(But I do not know how to instruct it to do so). From the waveform of example from AN351, 8 words can be read from SDRAM consecutively. Just like what Kenland has done, I tried to use "pointer++" to get consecutively located data from SDRAM, the simulation result disappointed me down to hell: a word would return from SDRAM every more than 5 clock cycles(I did not calculate the exact cycles). During this workday, I will try dma. Thank you, Kenland & Clancy!