What's the burst length of SDRAM in Nios II?

The burst length in Altera's Avalon SDRAM controller is fixed at 1, it cannot be changed. Reading/writing at consecutive addresses in SUSTAINED mode will take one clock cycle per operation (or very close to), this is as good as burst mode. If you are accessing random locations (on different SDRAM rows/banks), there will be an overhead due to opening/closing the rows/banks, which will not disappear even if you set bursts>1. In fact, in some cases (no cache hits for example), random access performance will be even worse with bursts>1. These are common problems with any system using SDRAMs and the performance issues you see are not particularly specific to Altera's controller (although some minor optimizations could be done, I think).

Some things you can do:

- enable DMA

- use instruction and data caches (experiment with different sizes)

- use register variables in your code - in extreme cases, use an additional fast SRAM or on-chip RAM to store variables you access more frequently

- do application specific hardware accelerators (peripherals or custom instructions) to speed up certain parts of your design - like a simple dedicated cache for an array, as an example