What's the burst length of SDRAM in Nios II?

I've done a bit of work trying to get performance out of the Altera SDRAM controller. I'm using the same 16MB 32 bit wide Micron chip as the Cyclone devkit board.

Using dma, and with help from Altera, I've been able to *write* sdram at essentially one clock per write for lengths up to 480 writes. So emptying my external lpm_fifo takes about 485 clocks to empty.n(@75MHz)

This is while running out of the same sdram and operating on other data simultaneously. So its pretty optimal.

Now for the bad part http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif

any code such as my_array[i] or *my_array_ptr++ is very slow. Writing memory useing these common techniques results in 5 clocks per write. I haven&#39;t really studied the compiled assembly but this is devastating for my application.

One thing is, I don&#39;t see any instruction that increments the register as the read or write is performed like on other processors I&#39;ve worked with. Without this, reads and writes effectively take multiple clocks *no matter how fast* the memory is or how good the controllers burst behavior.

So really, until there is some more work at the instruction + compiler level, performance is going to be illusive. If you can do things in chunks with no need to modify each word, you can use dma.

Anyone know any different? Or have a custom instruction for fast reads/writes?

Ken