Forum Discussion
Altera_Forum
Honored Contributor
10 years agoIf you select create simulation model, Qsys will generate the simulation friendly RTL only and you will need to write your own testbench with clocks and resets.
If you select create testbench system, Qsys will generate simulation friendly RTL plus a testbench wrapper that instantiate your Qsys system and BFMs for clocks and resets. It will produce 4 folders: mentor, aldec, cadence and synopsys each for different simulators.