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Altera_Forum
Honored Contributor
13 years agoRemember PCIe is a networking protocol, not a bus protocol!
I PCIe write is sent as an hdlc frame containing the address and data (typically upto 128 bytes worth), when the target has completed the action it sends back response packet. This means that there is a moderate amount of 'software' (usually a big state engine) associated with the PCIe interface. This is also why, although PCIe is high throughtput, it is often also high latency. This matters when the cycle is expected to be synchronous - eg when a cpu is reading a device register.