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So can I understand like PCIe includes both software and hardware. One of its component is gigabit transceiver?
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A generation 1, single lane, PCIe interface (gen1 x1 PCIe) uses a single transceiver, i.e., a differential transmitter and a differential receiver (4 pins on the FPGA). The transceiver lanes operate at 2.5Gbps. The PCIe interface also needs a 100MHz clock, PCIe reset, and a few other signals (depending on your application).
PCIe can use more than 1 lane, eg., x4 (by-4) uses 4 transceivers, x8 uses 8 transceivers. Newer generations of PCIe use faster lanes, eg., gen2 5Gbps and gen3 8Gbps.
You should try reading the PCIe Megacore users guide. I'm sure it explains it :)
Cheers,
Dave
Honored Contributor
