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Altera_Forum
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16 years ago

What frequency do you run Nios at?

I'm using the Nios-II processor on several projects using the Cyclone III FPGA (slowest speed grade). I generally run at a frequency of 100MHz and have been able to do this with some mild effort.

I'd love to push this faster, but am not sure what I can reasonably expect to achieve. Just so I can get a sense of what other people are doing on similar hardware, would you please post your experiences.

Myself, I'm running at 100MHz using the Cyclone-III (speed grade 8). I use the Nios-II/f processor with floating point support. I have a handful of custom instructions and some fairly complex peripherals hanging off the main bus. I haven't tried all that hard to push the frequency higher, but it's on my todo list and I'd like to know what others have achieved.

Thanks

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Hello,

    After compilation, you can go to the report of TimeQuest Timing Analyzer, under slow and fast model you have an estimation of the maximum frequency you can use.

    Anyway, you can try to increase the frequency and Quartus will tell you when setup or hold timing are violated.

    Jérôme
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Will it report a (meaningful) error/warning if a combinatorial custom instruction is too slow ?

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    The custom instructions are part of the project, so there are also analysed like the other blocks. So if timing requirements are violated, there will be reported.

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Right, I'm mostly wondering how fast others have been able to run the Nios-II processor on a cyclone III platform. I'm finding 100MHz is definitely doable. Is anyone pushing 150MHz?

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    167MHz is doable on the Nios embedded eval kit (NEEK). It could go higher but then you would be running the external memory out of spec. That's a 6 speed grade so on the slowest speed grade of 8 I would expect the fastest would be around 120-130MHz assuming you architect your system for frequency instead of latency.

    Yes custom instructions can become part of the critical path. You can determine if they are by showing the complete timing path and checking to see if the custom instruction logic is part of it. You should see the start and end of the path being the Nios II pipeline (or the on-chip memories that form the CPU registers) with the custom instruction somewhere in between. If achieving a high frequency is important and the custom instruction is in the critical path then consider pipelining the custom instruction.

    Of course it doesn't make any sense to look into any of this unless you have constrained your design. If you haven't then I recommend that be your first step so that your I/O timing can be traded off with the on-chip timing properly by the fitter and timing analysis. I recommend using Timequest for this as it will give you better results than the classic timing analysis tool.