Occasional ContributorWhat are the control register descriptions for Frame Buffer IP (V13.1)?
Hello,
We are creating a video streaming pipeline using Altera IP cores and a Cyclone V FPGA. Our pipeline currently consists of a sensor, Clocked Video Input IP (V14), Frame Buffer IP (V13), and on-chip memory.
Our current behavior shows non repeating data being loaded into on-chip memory; however, our register reads give confusing results. Using NIOS II we read the run-time writer control port from the Frame Buffer IP and get the following data.
Register 0 : 1h
Register 1 : 1h
- starts out at 0h and increments once
Register 2 : 2h
- starts out at 0h and increments twice
Register 3 : 2ch
- starts out at 0h
- starts increment after Register 2 reaches 2h
Available documentation varies and is vague. Some documentation would suggest that we load two frames, and then drop the rest. However, I've seen one instance of Register 2 being listed as an Interrupt Register, and Register 3 as the Frame Counter.
Additionally, frame dropping is enabled in the Frame Buffer IP GUI. Prior to frame dropping being enabled, the CVI IP would indicate an overflow after passing 2 frames.
Can anyone confirm what the registers are for our version of the Frame Buffer IP? And in the case that we are in fact dropping all our frames due to an over flow issue, are there suggestions on how to fix this?
