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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

weird timer & uart behavour

Hi guys, could anybody tell my why my code hang up when I switch the

sys_clk_timer from NONE to SYS_CLK or when I switch stdin and stdout from

NONE to UART_0 in the BSP-Editor ???

That's really weird !?!

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    This could be due to the system clock timer being very low, by default it is 1us. I think when you enable sys_clk_timer to SYS_CLK, it will generate an interrupt for every 1us and the NIOS takes ~15us to service the interrupt. This will flood the NIOS with interrupts. Option is to increase the value of system clock timer in the SOPC builder to 1 ms or greater so the NIOS will have enough time to service it.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    Thank's for your reply...

    I have a clock period of 10ms. In SOPC I've choosen the option "simple timer interrupt". Do I need a specific code part to enable the timer in NIOSII? I simply want to read the time after start with alt_nticks()...