Honored Contributorwaitrequest signal for Avalon MM Slave
I have created a custom Avalon MM Slave component with SOPC v10.1 which uses chipselect_n, read_n, write_n, address/data, and waitrequest. Long story short I need it to be variable wait states so that's why I need the waitrequest signal. In my first implementation my slave logic asserts waitrequest asynchronously when selected (based on chipselect_n) and then de-asserts when my Slave has the data ready. But in signal tap I see the chip select from the master never deasserts and the R/W hangs (using FS2 console the indication is that the CPU is hung). so my question is how can I assert waitrequest asynchronously (as the avalon spec shows) and then deassert it synchronously based on my logic? I had written this very simple snippet that does not work because when "my_logic_done" goes high...chipselect is still low and so the async preset takes priority. any way around this? the big issue is that the Avalon spec shows the waitrequest immediately (async) with read/write/chipselect.
process (rst_n, chipselect_n, clk) begin if (rst_n = '0') then waitrequest = '0'; elsif (chipselect_n = '0') then waitrequest = '1'; elsif rising_edge (clk) then if (my_logic_done = '1') then --this is a single clock-wide pulse waitrequest = '0'; end if; end if; end process; any ideas??
