waitrequest signal for Avalon MM Slave

The nios cpu always asserts all 4 byte enables during read cycles - it discards the unwanted bytes internally. For writes is only asserts the required byte enables.

This means that the bus width adapter inserted before an 8-bit slave will always generate 4 read cycles. (For writes, it might generate the cycles with no byte enables!)

The usual way around this is to make the device be a 32bit slave that ignores the high bits.