Honored Contributor
Honored ContributorIf you use the Avalon bus to connect the RAM, it makes no difference (but performance) to the other parts of the design, what RAM technology is used.
The Avalon bus can do Multi-Master, so sharing the RAM between multiple parts of the design (CPU, Ethernet DMA-controller, your own "hardware") is possible. I don't see a predefined way to share the TSE (or whatever Ethernet controller) between the CPU and some "hardware" you design. Perhaps another idea is to implement a second Ethernet IP core and use a switch chip with two MII interfaces as a Phy to allow for a single cable. Do you really need GBit ? If no, I suppose using the OpenCore Ethernet controller would be a better idea, as you might be able to modify it in a way that is better suited to interface with your "hardware". Any standard Ethernet core would need a CPU interface, additionally, for configuration purpose. Do you really want to do the (UDP / ) IP stack in "hardware" (how, if I may ask) ? If no, maybe a second NIOS running a Niche stack might be way to avoid the Linux overhead for the "realtime" network access. If doing this you maybe could avoid the second Ethernet controller by creating a pure software IP layer interface between the Linux system and the second NIOS. -Michael
