Forum Discussion
6 Replies
- Altera_Forum
Honored Contributor
What device has been mapped at that address range?
- Altera_Forum
Honored Contributor
Since that is a 32 byte address range, and the jtag loader only reports the entire range (not where it got the first error), I suspect that is one of the interrupt vector/rest locations.
- Altera_Forum
Honored Contributor
It's the
reset 0x04011800 - 0x0401181F epcs_flash_controller 32 0 But I didn't change anything on both project. So why it's stop working? - Altera_Forum
Honored Contributor
And I checked the EPCS with the Terasic control panel
- Altera_Forum
Honored Contributor
If the reset vector is inside the epcs_flash_controller, I don't think your program image should have any code for that address.
Something will have gone wrong inside all the 'magic' that attempts to make building a loadable image easy. The images I build are so dissimilar from those the IDE generates I couldn't even comtempate beating it into submission. Not only that, we download the code from system filestore - so the system used to compile to code doesn't need any of the Altera software installed - just gcc for nios2. - Altera_Forum
Honored Contributor
--- Quote Start --- It's the reset 0x04011800 - 0x0401181F epcs_flash_controller 32 0 --- Quote End --- This is the nios bootloader address (I thought this was excluded from verification, but probably I was wrong). Do you use a standard bootloader? Check if you changed the epcs_controller_boot_rom.hex file in the Quartus project. You can regenerate the file by rebuilding the Qsys module.