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Altera_Forum's avatar
Altera_Forum
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15 years ago

Vectored Interrupt Controller implementation

Sorry if this is a basic question, but I couldn't find an answer in the literature or forum. I've implemented a VIC in the SOPC Builder, but after generation I now have a d_irq_to_the_cpu_0 in...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I have the same problem. Can I just ignore this input port or will VIC not function properly?