Using SDRAM Controller on Development Board

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originally posted by jhansen@Jul 22 2005, 03:42 AM

use a dma to handle the transfer from converter to memory.

then you have a shared resource with two masters, processor and dma.

you can setup priority on each to ensure bandwidth.

12.5 mhz on a 50mhz system gives a load of 25 - 35 % including overhead, that looks ok if hte processore does not use nore than the rest.

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Would the DMA transfers between the A/D and SDRAM be handled by the Nios II core or would a separate DMA controller generated using SOPC act as the 2nd master with the SDRAM providing slave-side arbitration between the Nios II and DMA controller?

Also, how difficult is it to create custom FPGA circuitry that interface to the avalon-based DMA controller that transfer data from a the A/D-samples FIFO @ 12.5 MHz and store it on the SDRAM within a specified address range? Effectively you would have the DMA controller master facilitating the transfer between two slave devices (A/D & SDRAM).

Brad.