Using Nios II with PLL

OK - the project you attached fundamentally works - more or less...

I ported it to a DE0-Nano with no changes, except for the device and pinout. In doing so I notice you'd exported the PLL's reset ("altpll_0_areset_conduit_export") but not constrained it to a pin. So, Quartus has chosen a pin which, I suspect, you're not controlling. So, it's probably pulled high holding the PLL in reset.

I connected that to a switch and proved this. Providing the PLL is out of reset (reset driven LOW), the processor boots and "hallo Welt>!Init Phase...." is written to the console. I'm confident (although I didn't try it) that it will work at 100MHz as well.

I expect you have the same issue with your MAX 10 project.

Cheers,

Alex