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Honored Contributor
Honored ContributorUsing Nios II with PLL
Hello there, so I´m trying to generate 100MHz from 50MHz via the ALTPLL in Qsys and use that 100MHz to speed up the NiosII. Unfortunately its not working... Im Using a 10M16DCF256I7 and ...
Altera_ForumHonored Contributor
Honored ContributorThank you very much for your response,
i created a sdc file with those parameters: create_clock -name {CLOCK50MHz} -period 20.000 [get_ports { clk_clk }] derive_clock_uncertainty derive_pll_clocks The TimeQuest report says, that fmax could be 117 MHz on the PLL Clock and 250MHz on the input clock *the logic only consists of the nios system there is nothing else in the design
