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Altera_Forum
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10 years ago

Using Nios II with PLL

Hello there, so I´m trying to generate 100MHz from 50MHz via the ALTPLL in Qsys and use that 100MHz to speed up the NiosII. Unfortunately its not working... Im Using a 10M16DCF256I7 and ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Will your logic run at 100MHz? Have you constrained your project, told Quartus about the 50MHz clock and derived clocks? Did Quartus report it could meet timing?

Those devices can and will run logic at 100MHz, depending on the complexity of the design. Qsys systems with a Nios processor can result in (relatively) complex logic that simply may not run at 100MHz. If so, I'm afraid it's not going to work.

Ensure you've constrained your design and note whether it meets timing - having run it through Quartus.

Cheers,

Alex