User Peripheral simulation in ModelSim

Hello,

I have a problem by User Peripheral simulation in ModelSim.

SOPC consists of:

Nios2

jtag_uart

OnChip memory

my own very simple component (Avalon slave user peripheral, simulation allowed)

The component was already tested separately in Quartus simulator.

In the Nios IDE, I have "Hello World" program written. With "Run as Nios II ModelSim" it was simulated sucsessfull.

But if I was expanding the program and access my periphery, I get the message in Modelsim "WARNING: cpu_0_test_bench/A_wr_data_unfiltered is 'x' ". The simulated signals show that on the Avalon bus everything is correct (data, address, clock, chipselect, etc.). However, all periphery signals remain undefined.

What could be the problem?