Has anyone had any experience with interfacing to an external (to the gate array) USB Chip ? I am looking for a simple, cheap, low power chip that interfaces directly to a NIOS or even better to Internal Memory. I know that there are USB controllers available that will do the job (I am currently looking into an Cycpress chip that has a 8051 controller, and it will do the job, however it might be a little "over kill". We don't need as many features as are offered there in!). We have also investigated a USB-to-serial chip which will also do the job, but we would prefer a direct USB connection. Anyone got any ideas ?

--- Quote Start --- Has anyone had any experience with interfacing to an external (to the gate array) USB Chip ? I am looking for a simple, cheap, low power chip that interfaces directly to a NIOS or even better to Internal Memory. I know that there are USB controllers available that will do the job (I am currently looking into an Cycpress chip that has a 8051 controller, and it will do the job, however it might be a little "over kill". We don't need as many features as are offered there in!). We have also investigated a USB-to-serial chip which will also do the job, but we would prefer a direct USB connection. Anyone got any ideas ? --- Quote End --- Your decision needs to be based on the interface speed you need. The FTDI FT245 and FT2232 series have parallel FIFO modes that can be used to send traffic at 1MB/s (asynchronous FIFO mode) and 25MB/s (synchronous FIFO mode). The Cypress FX2 is a USB 2.0 device with a pretty flexible general purpose bus interface. Unfortunately, it has an 8051 as a processor. Its not exactly the nicest processor to code and run an RTOS on. The Cypress FX3 looks pretty nice. There is a new board from Arrow called the BeUSB 3.0 which plugs into the BeMicro-SDK and BeMicro boards. http://components.arrow.com/manufacturers/cypress-semiconductor/ I purchased one, but have not had time to play with it. Yes, this is also probably overkill, but its another option to consider ... Cheers, Dave

The two FTDI parts suggested by dwh get my vote as they're just a (parallel) hardware interface and require no programming. The FT2232H can now hit rates of ~35MB/s using the latest driver.

Thanks for all your informative answers :). As an option, can any of these solutions be implemented without a NIOS and interfaced to memory internal to the SOPC builder via VHDL code? I am looking to cut power as much as we can. However I am not certain if such a design will in fact take so much less power? I assume that if we use a USB controller like the FX2 with the 8051 built in, it will be able to transfer the USB data to my memory internal to the SOPC system with no other internal interfacing required thus reducing the power requirements ? However there may be additional glue logic needed since there will be another NIOS attached this this internal memory and thus some sort of arbitration will be required. See the thread below http://www.alteraforum.com/forum/showthread.php?p=155961#post155961 (http://www.alteraforum.com/forum/showthread.php?p=155961#post155961) So I am not sure at this point which options will give the lowest power options ….? Also, speed is still an issue as it will be important for future designs where we plan to use\port this design there. Do you have any further suggestions ?

You'll probably need latch the data from the USB parrallel bits and request Avalon master bus cycles based on the latched values. In some senses a UART interface might make this easier - split each uart data byte into two 4-bit fields, use one as 'command', the other as 'data'. So a memory write would require upto 8 bytes to set the address, 8 bytes for the data and a final 'write' command (which might increment the address, and might set the last data nibble). Read would be much the same except that you'd send 8 data bytes to the host. That would be moderately slow - but probably not impossibly slow! The shared memory access isn't an issue. All the internal memory is dual-ported and the Avalon 'bus' does arbitration.

--- Quote Start --- As an option, can any of these solutions be implemented without a NIOS and interfaced to memory internal to the SOPC builder via VHDL code? --- Quote End --- Yes. I've written UART-to-Avalon-MM and FTDI FIFO-to-Avalon-MM master components. They implement an ASCII parser, so you can simply type "r <addr>\n" to read an address and "w <addr> <data>\n" to write an address. This interface is not exactly high-speed, but its good enough for debug. A higher-speed interface would just need to use a slightly more complex protocol, eg., binary packets, much like the JTAG-to-Avalon-MM interface. --- Quote Start --- I am looking to cut power as much as we can. However I am not certain if such a design will in fact take so much less power? --- Quote End --- Why are you using an FPGA if you are concerned about power? --- Quote Start --- I assume that if we use a USB controller like the FX2 with the 8051 built in, it will be able to transfer the USB data to my memory internal to the SOPC system with no other internal interfacing required thus reducing the power requirements ? --- Quote End --- No matter what, you will always have to implement some logic in the FPGA. Any external device has interface timing requirements that need to be met. --- Quote Start --- However there may be additional glue logic needed since there will be another NIOS attached this this internal memory and thus some sort of arbitration will be required --- Quote End --- That is why you should implement the logic as an Avalon-MM master. --- Quote Start --- Also, speed is still an issue as it will be important for future designs where we plan to use\port this design there. --- Quote End --- What is the speed requirement? Cheers, Dave

USB External Chip | Altera Community

15 Replies

Altera_Forum
Honored Contributor
13 years ago
--- Quote Start ---
We are about to get a FT232H module in which we are hoping to be able to connect up to one of our current gate arrays. This chip has FIFO 245 interface!

--- Quote End ---

I haven't used that particular device - but looking at the data sheet, I agree it should work fine.

--- Quote Start ---

Yes I am comfortable working with VHDL. Are you able to send me your design?
--- Quote End ---

Yeah, sure. Let me review/clean-up the documentation I'd started, and I'll post a zip file or a link to a zip file. I'll look at it tonight.

Cheers,
Dave
Altera_Forum
Honored Contributor
13 years ago
Dear Dave,

--- Quote Start ---
Let me review/clean-up the documentation I'd started, and I'll post a zip file or a link to a zip file.
--- Quote End ---

Did you end in the end manage to make the zip file and documentation ? Are you able to send it to me ?

Best regards

Shmuel
Altera_Forum
Honored Contributor
13 years ago
Hi Shmuel,

--- Quote Start ---

Did you end in the end manage to make the zip file and documentation ? Are you able to send it to me ?

--- Quote End ---

Sorry, I have been busy with another aspect of the project I am working on. I plan on using the FT232H on my board, so I will be returning to the code soon.

Have you tried writing some code? If you have, and you have had problems, post questions.

Cheers,
Dave
Altera_Forum
Honored Contributor
13 years ago
Dave,
Thanks for the reply. Please let me know when you get back to it and if you can send me something to look at. In the mean time I have started on the design myself..... We are considering using the FT2232H chip probably. Have you any good suggestions of how to implement interrutps ? We were thinking of usinging a dedicated endpoint for this purpose (I found out from FTDI they have 2 IN endpoints and 2 OUT endpoints !)

Regards

Shmuel
Altera_Forum
Honored Contributor
13 years ago
--- Quote Start ---

I have started on the design myself..... We are considering using the FT2232H chip probably. Have you any good suggestions of how to implement interrutps ? We were thinking of usinging a dedicated endpoint for this purpose (I found out from FTDI they have 2 IN endpoints and 2 OUT endpoints !)

--- Quote End ---

You don't need to do anything at the USB end, that is the point of using these devices :)

The FT2232H will show up as two serial ports. Your host code can access them just like it would a USB-to-serial serial port. Under Linux they will show up as /dev/ttyUSBx devices, and under Linux as COM port devices.

At the FPGA end, you just need to implement the FIFO interface to your hardware. The SIWU (send-immediate/wake-up) signal can be used to trigger the data to be sent 'faster', i.e., send-now, rather than waiting for a full USB packet to be buffered.

Did you order an evaluation kit? FTDI have a module FT2232HQ_mini_module for $27

http://www.digikey.com/product-detail/en/ft2232h%20mini%20module/768-1030-nd/2027252

I haven't tried interfacing to this board yet (I have a module I was given at ESC, but have not had time to test it). I have used the UM245R module, and it was easy to work with. I have a couple of the FT232H modules that should show up in a couple of days.

Cheers,
Dave

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USB External Chip

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