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You don't need any special component. The fabric will connect the masters and the slaves together.
The data bus is usually 32 bits, so the DMA can transfer 4 bytes per cycles. Your calculation is assuming that the ram can take one word per cycle, and this of course depends on the type of RAM and the kind of transfer. A DMA transfer can use burst transfers, so most DRAMs will be very fast with this kind of transfer.
If the Nios CPU is trying to access the SDRAM, it will be shared with the DMA master, so the DMA throughput will decrease. IIRC you can adjust priorities for both masters, or if you design your own component with an Avalon master, you can lock the arbiter to be sure you have exclusive access to the memory during the transfer.
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Thank you for your kind answer... Now it is much more clear... One last question If I will use another SDRAM chip with dedicated SDRAM controller. So in other words one SDRAM for NIOS and one SDRAM for samples I can achieve absolutely background transfer of the samples without any sharing.. Am I right?
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