Usage of DMA from PIO to SDRAM shared by NIOS

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Yes, the Avalon fabric will share the SDRAM between the processor and the DMA.

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Thanks for the answer. Just for ensure myself. My system will get some commands from the TCP and in the message receiving task it starts the DMA transfer like this:

My SDRAM is mapped in the address space from 0x08000000 till 0x0FFFFFFF ( 128 MB ). Now I want to start DMA transfer from the PIO which is directly connected to the dma read_port to the SDRAM somewhere for example from 0x08300000. The write_port of the dma is connected to the SDRAM. The SDRAM is also connected to the NIOS. Please see attached .qsys file (just to be sure that everything is OK).

No I am writing to the DMA_0_BASE register number 2 the write address, I have used 0x00300000 - relative a dress in the SDRAM. Am i right?

          IOWR(DMA_0_BASE,1,0);
          IOWR(DMA_0_BASE,2,0x00300000);
          IOWR(DMA_0_BASE,3,20);
          IOWR(DMA_0_BASE,6,0x00000182);
          IOWR(DMA_0_BASE,6,0x0000018A);

The end of the transaction is checking by reading the length register IORD(DMA_0_BASE,3) until it equals 0. Afterwards I am reading the data section by:

  for(i=0;i<20;i++)
          {
              sample_ddr = IORD(SDRAM_BASE,0x00300000+i);
              sample = sample_ddr&0x0000FFFF;
              sample = sample_ddr>>16;
              printf("%4d\n%4d\n",sample,sample);
          }

But in the terminal the content of the SDRAM has not changed, it is the same one like before the transaction. I am not sure if I am handling the addresses of the write and read part correctly. Would you be so kind and check this think out?

Thank you so much, you are so kind...