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Contributor

4 years ago

Updating NIOS SW without touching FPGA Programmable logic

Hi All, We are rapidly changing the NIOS SW without any changes in FPGA programmable logic. Is there a way to say to Quartus do not to change (do not touch) the FPGA programmable logic at all an...

amildm

Contributor

4 years ago

Cool... So, as for the JIC generation, should both SOF and HEX files be the input files?

What actually happens during the JIC file generation? How does it mix the SOF and HEX files?

EBERLAZARE_I_Intel
Regular Contributor
4 years ago
Hi,

Yes, the .sof, .hex are the input files, and the .pof generated:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/nios2/edh_ed_handbook.pdf#page=286

See the example here:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/nios2/edh_ed_handbook.pdf#page=261
- amildm
  Contributor
  4 years ago
  OK, the *.POF is for MAX devices... What's the flow for the *.JIC devices (e.g. Cyclone 10)?
  
  Should not I deal with a bootloader in order to load two images from FLASH (the first image is for FPGA programming, the second one is for NIOS SW)?

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Updating NIOS SW without touching FPGA Programmable logic

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