unstable-nios2mmu boot error
Hi all,
Here is what I try to do :
- I have a SOPC system with a NIOS2 with MMU. It is configured exactly as explain in : alterawiki.com/wiki/Linux_for_the_Nios_II_Processor
- I want to use device-tree so I use the kernel branch unstable-nios2mmu as suggested in the same link : alterawiki.com/wiki/Linux_for_the_Nios_II_Processor
When I try to make my Linux boot I got the following :
fault during kernel misaligned fixup @ 0xd0212794; addr 0x00000003; isn=0x20800017
Linux version 2.6.39-rc3-01078-gaf7b9ea-dirty (ben@debian) (gcc version 4.1.2) #21 Thu May 12 14:31:53 CEST 2011
bootconsole [early0] enabled
early_console initialized at 0xe4842020
On node 0 totalpages: 4096
free_area_init_node: node 0, pgdat d04d66a8, node_mem_map d04f1800
DMA zone: 32 pages used for memmap
DMA zone: 0 pages reserved
DMA zone: 4064 pages, LIFO batch:0
pcpu-alloc: s0 r0 d32768 u32768 alloc=1*32768
pcpu-alloc: [0] 0
Built 1 zonelists in Zone order, mobility grouping off. Total pages: 4064
Kernel command line:
PID hash table entries: 64 (order: -4, 256 bytes)
Dentry cache hash table entries: 2048 (order: 1, 8192 bytes)
Inode-cache hash table entries: 1024 (order: 0, 4096 bytes)
Memory available: 11144k/5039k RAM (2107k kernel code, 2932k data)
NR_IRQS:32
Unable to handle kernel NULL pointer dereference at virtual address 00000000
ea = d0212b98, ra = d0212b98, cause = 14
Kernel panic - not syncing: Oops
I don't know where is the issue (hardware design, kernel, erroneous device-tree).
Maybe that comes from the first "error" I get : fault during kernel misaligned fixup @ 0xd0212794; addr 0x00000003;
Does someone has any idea ?
Best regards
See attached for the device tree
My nios.h (you still need to modify it) :
Code:
#ifndef _ASM_NIOS2_NIOS_H
#define _ASM_NIOS2_NIOS_H
/* Add some defines wich should REALLY be extracted from fdt */
/* ==> REMOVE */
#define DDR2_TOP_BASE 0x10000000
#define DDR2_TOP_SPAN 16777216
/* <== END REMOVE */
/*
* Maximum possible cache sizes on the Nios II. Only used in head.S where
* the information from cpuinfo is not yet available.
*/
#define NIOS2_DCACHE_SIZE 2048
#define NIOS2_ICACHE_SIZE 4096
/*
* Minumum possible cache line sizes on the Nios II. Only used in head.S
* where the information from cpuinfo is not yet available.
*/
#define NIOS2_DCACHE_LINE_SIZE 32
/* Nios II instruction cache line size is always 32 bytes */
#define NIOS2_ICACHE_LINE_SIZE 32
#define NIOS2_ICACHE_LINE_SHIFT 5
#endif /* _ASM_NIOS2_NIOS_H */