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A timing analysis was done and there was no change we are aware of to the timing models in going to the new process. According to PCN0904, it is the same in form, fit, and function with the existing data sheets.
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Is the SDRAM clock single-data-rate (SDR) SDRAM? Is the FPGA generating the clock? Did you have to change the timing of the clock to the SDRAM to get it to work?
Have you probed with a scope to check the timing of the 'working' board versus the new devices?
I'm just wondering whether the timing on the first board was marginal, and now things are properly broken. Have you tried moving the SDRAM clock around (using a PLL phase shift) to see what sort of setup/hold timing margin you have?
Cheers,
Dave
Honored Contributor
