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It seems that the boards which displayed this problem had Cyclone processors which went from a 65 nm to a 60 nm process. When we downgraded our clock rate for the SDRAM the problem went away.
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Do you use TimeQuest for timing analysis?
If not, you should perform a timing analysis with both boards.
Ideally the change in process should be reflecting in the change in FPGA timing. You should be able to get both boards operating with the same SDRAM clock frequency, but you might need to adjust output timing to different 'optimal' values for each board type.
Cheers,
Dave
Honored Contributor
