Forum Discussion
Altera_Forum
Honored Contributor
13 years agoI don't think it is a cache issue because I only access SDRAM with the IOWR and IORD commands. The code is very simple and never access to SDRAM by another way.
And even no access to SDRAM, a lot of memory cells content are changed at every step (using F5 step with debug) and that have no sense for me! I will try using pointers