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Honored Contributor
Honored ContributorUnable to use Nios II/e?
I've been trying to instantiate a Nios II/e core with no success. I am using external SRAM, one 16 bit PIO, and a 50Mhz clock. I am able to synthesize the design, generate the sof file, and con...
Altera_ForumHonored Contributor
Honored ContributorIt's the other way round, the JTAG module is a slave. You'd need to so something like:
Nios Instruction master + Nios data master -> Pipeline Bridge -> JTAG debug module. It's a good idea to try to do a minimal system that still reproduces the problem, it can make it easier to debug. Could you also add a small signaltap instance (that for example monitors the reset signal) and try to connect to it once the FPGA is programmed? That way we can determine if the problem comes from the Nios CPU itself or the JTAG interface. The LED pios are easy to constrain, just declare them as false paths so that Timequest doesn't verify their timing. But if this is the only error that Timequest gives then you have nothing to worry about, timing wise.
