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Honored Contributor
Honored ContributorUnable to boot from on-chip RAM
Hi, I am using QuartusII version 11.1. I have designed a custom board with Cyclone IV E FPGA, EPCS16 configuration device, character LCD and some other ICs. I could successfully build a Qsys ...
Altera_ForumHonored Contributor
Honored ContributorHi dsl,
The problem was not with the JTAG module. The culprit was the cpu's jtag_debug_module_reset signal. I had connected it to the cpu's reset_n signal in Qsys. It was a loopback connection in addition to the clk_reset signal coming to the cpu. When I removed the connection from jtag_debug_module_reset, I no longer faced any issue, even if the JTAG UART block is present in the system.
