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Altera_Forum
Honored Contributor
12 years agoHi dsl,
The problem was not with the JTAG module. The culprit was the cpu's jtag_debug_module_reset signal. I had connected it to the cpu's reset_n signal in Qsys. It was a loopback connection in addition to the clk_reset signal coming to the cpu. When I removed the connection from jtag_debug_module_reset, I no longer faced any issue, even if the JTAG UART block is present in the system.