Honored Contributor
Honored ContributorI have checked the reset vector of the CPU. It is pointed correctly to the start of onchip_mem.
I am doubting the clk_reset signal connected in Qsys. The documentation for clk_0 says that "Clock output interfaces cannot have reset signals". I can't understand what this is trying to say. Does this mean that externally applied reset, which is made to pass through the clock block doesn't propagate to the modules in Qsys. This is what I observe in practise. NiosII doesn't jump to the reset location when I press the reset button on the board, but the JTAG interface is able to reset the processor.
