uClinux TSE not working

Thank you Kazu for helping me! :)

module uClinux(
	// Clock
	input  CLOCK_50,
	
	// KEY
	input   KEY,
	
	// Ethernet 1
	output        ENET1_GTX_CLK,
	output        ENET1_MDC,
	inout         ENET1_MDIO,
	output        ENET1_RESET_N,
	input         ENET1_RX_CLK,
	input   ENET1_RX_DATA,
	input         ENET1_RX_DV,
	output  ENET1_TX_DATA,
	output        ENET1_TX_EN,
	
	// SDRAM
	output		  DRAM_CLK,
	output DRAM_ADDR,
	output   DRAM_BA,
	output        DRAM_CAS_N,
	output        DRAM_CKE,
	output        DRAM_CS_N, 
	inout   DRAM_DQ, 
	output   DRAM_DQM,
	output        DRAM_RAS_N,
	output        DRAM_WE_N,
	
	// RS232
	input         UART_RXD,
	output        UART_TXD
);
	wire sys_clk;
	wire enet_tx_clk_125, enet_tx_clk_25, enet_tx_clk_2p5, tx_clk;
	wire enet_gtx_clk_125, enet_gtx_clk_25, enet_gtx_clk_2p5;
	wire core_reset_n;
	wire mdc, mdio_in, mdio_oen, mdio_out;
	wire eth_mode, ena_10;
	assign mdio_in   = ENET1_MDIO;
	assign ENET1_MDC  = mdc;
	assign ENET1_MDIO = mdio_oen ? 1'bz : mdio_out;
	
	assign ENET1_RESET_N = core_reset_n;
	
	assign DRAM_CLK  = sys_clk;
	
	assign ENET1_GTX_CLK = eth_mode ? enet_gtx_clk_125 :       // GbE Mode   = 125MHz clock
								  ena_10   ? enet_gtx_clk_2p5 :       // 10Mb Mode  = 2.5MHz clock
	                       enet_gtx_clk_25;         			  // 100Mb Mode = 25 MHz clock
	pll pll_inst(
		.areset	(~KEY),
		.inclk0	(CLOCK_50),
		.c0		(sys_clk),
		.c1		(enet_tx_clk_125),
		.c2		(enet_tx_clk_25),
		.c3		(enet_tx_clk_2p5),
		.locked	(core_reset_n)
	);
	
	enet_pll_90 gtx_pll_inst(
		.areset  (~KEY),
		.inclk0	(CLOCK_50),
		.c0		(enet_gtx_clk_125),
		.c1		(enet_gtx_clk_25),
		.c2		(enet_gtx_clk_2p5),
		.locked	()
	);
	
	assign tx_clk = eth_mode ? enet_tx_clk_125 :       // GbE Mode   = 125MHz clock
	                ena_10   ? enet_tx_clk_2p5 :       // 10Mb Mode  = 2.5MHz clock
	                           enet_tx_clk_25;         // 100Mb Mode = 25 MHz clock
	
	
	nios_system system_inst (
		.reset_reset_n	(core_reset_n), 
		.clk_clk		(sys_clk), 
		
		.sdram_wire_addr		(DRAM_ADDR), 
		.sdram_wire_ba		(DRAM_BA),
		.sdram_wire_cas_n	(DRAM_CAS_N), 	
		.sdram_wire_cke		(DRAM_CKE), 		
		.sdram_wire_cs_n		(DRAM_CS_N), 			
		.sdram_wire_dq		(DRAM_DQ), 				
		.sdram_wire_dqm		(DRAM_DQM), 			
		.sdram_wire_ras_n	(DRAM_RAS_N), 			
		.sdram_wire_we_n	(DRAM_WE_N), 			
		
		.rs232_external_connection_rxd	(UART_RXD), 			
		.rs232_external_connection_txd	(UART_TXD),  			
		
		.tse_mac_conduit_connection_tx_clk 	(tx_clk), 				
      .tse_mac_conduit_connection_rx_clk 		(ENET1_RX_CLK), 		
      .tse_mac_conduit_connection_mdc        (mdc),             	
      .tse_mac_conduit_connection_mdio_in    (mdio_in),           
      .tse_mac_conduit_connection_mdio_out   (mdio_out),         
      .tse_mac_conduit_connection_mdio_oen   (mdio_oen),         
      .tse_mac_conduit_connection_rgmii_in   (ENET1_RX_DATA),    
      .tse_mac_conduit_connection_rgmii_out  (ENET1_TX_DATA),    
      .tse_mac_conduit_connection_rx_control (ENET1_RX_DV),       
      .tse_mac_conduit_connection_tx_control (ENET1_TX_EN),      
      .tse_mac_conduit_connection_eth_mode   (eth_mode),        
      .tse_mac_conduit_connection_ena_10     (ena_10)          			 
    );	
endmodule