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Hi,
At first, please check whether the interrupt signal (irq No.2 in this case?) is asserted or not. This check is easily done by using your Signal Tap II.
Kazu
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Hi Kazu,
You are right about the irq signal isn't asserted. I took a screen shot of the signaltap II (attached) and find out the chip select and input clock isn't either. I use the PIO IP in the QSYS and configure it as follow.
clk -> 50Mhz PLL
s1 -> clock crossing bridge ->NIOS2 CPU data master bus
reset -> clock and jtag reset lines
external_connection -> ext_pins
The PIO configuration are
Width: 1
Input
Edge Capture regiser -> Synchronously capture (check) Edge Type: Rising
Interrupt: Generate IRQ (check) IRQ Type: Edge
Any help is greatly appreciated.
Thanks,
Yeung
Honored Contributor
