u-boot on the nios2 eval baord

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originally posted by smcnutt@Apr 14 2006, 10:33 AM

hi fmcmurra,

> but for some reason it i don't get anything out of the uart (not jtag uart).

> i single steped through the code and it appears to be in the main loop waiting

> for input.

make sure your clock setting is correct (config_sys_clk_freq). for the 'standard'

fpga configuration this should be 80 mhz (since the 24 mhz external clock is routed

to a pll). in the old versions of quartus, this was obvious since the pll was always

on the main schematic (bdf file). the new versions support the pll component in

sopc builder -- so it's real easy to overlook.

> is there something else i should be doing, besides enabling it in the config file?

not really -- i believe the baudrate is fixed at 115200 for the standard configuration.

you can try switching to the jtag uart -- if that works, your problem will be isolated

to uart1 ... if it doesn't, there's probably another problem.

> is it safe to assume my fpga doesn't have sram? i'm inclined to believe it does,

> but wasn't enabled. should i enable it?

i don't think the eval board has any external sram. you can create an on chip ram

with sopc builder if you like. it looks like there's plenty of memory left in the

standard configuration -- although it's not necessary for any of the nios-ii specific

code in u-boot.

regards,

--scott

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Got it! I had the clock set for 24MHZ. Are you sure it&#39;s 80MHZ. I seem to recal seeing 66MHZ in SOPC Builder.

If I didn&#39;t talk with you, how would I know to change the sys clk to 80MHZ.

What other got ya&#39;s are there?

Even if the sys clk was wrong I would still expect to see some garbage coming out of the UART. I&#39;ll make the clock chnage and if that doesn&#39;t fix it, I&#39;ll get out the scope to see if anything is wiggling on the TX pin.

Thanks for the help...