u-boot on the nios2 eval baord

This ddidn't get sent for some reason:

Hi fmcmurra,

> The one in the regular u-boot tree works just fine so I'm hoping this one does too.

See the reference above. Also ...

Thanks Scott,

I think I'll just hardcode the flashinfo until I get the board up and then I'll work on the CFI stuff.

The sources from psyent are from the "regular" u-boot tree -- in fact, the sources

from pysent are identical with the following exceptions:

Good job pruning this down and getting it to compile under Cygwin., that was a nontrivial task.

Probably the altera board directory is best -- perhaps the 1c20.

Ok, That's the one I chose as a model. I have it ported over, compiled and loaded into ram, but for some reason it I don't get anything out of the UART (not JTAG UART).

I single steped through the code and it appears to be in the main loop waiting for input.

As you know the eval board doesn't have the _real_ uart connected. It comes out to a MAX232 and terminates at the pads on the proto area. I added a connector and wired it up to a DB9 as a NULL modem. Serial comm is childs play to me so I know I have it wired up correctly. Is there something else I should be doing, besides enabling it in the config file?

Also, I noticed the other boards have the SRAM enabled. I looked at my system.h file and their is no mention of SRAM. Is it safe to assume my FPGA doesn't have SRAM? I'm inclined to believe it does, but wasn't enabled. Should I enable it?

Best Regards,

--Scott

BTW: I would encourage anyone interested in u-boot for Nios-II to apply some