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Altera_Forum's avatar
Altera_Forum
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12 years ago

Two x NIOS II boot from EPCQ in Quartus 13.1

Hello,

It seems that there are a bug in Quartus software for programming the EPCQ.

The following workaround (http://www.altera.com/support/kdb/solutions/rd11192013_118.html) provided by Altera solve the problem (at least for one NIOS II)

In my design I have two NIOS II's implemented in FPGA.

To program the FPGA configuration + first CPU + second CPU into the EPCQ, I followed the exact step provided in the above link with slight modifications (in red) as shown below:

Step 8.

a. sof2flash --input=hw.sof --output=hw.flash --epcq -verbose

b. elf2flash --input=sw1.elf --output=sw1.flash --epcs --after=hw.flash -verbose

c. elf2flash --input=sw2.elf --output=sw2.flash --epcs --after=sw1.flash -verbose

Step 9.

a. nios2-flash-programmer --epcs --base=0x4081000 --device=1 --instance=0 hw.flash

b. nios2-flash-programmer --epcs --base=0x4081000 --device=1 --instance=0 sw1.flash

c. nios2-flash-programmer --epcs --base=0x4081000 --device=1 --instance=0 sw2.flash

result: the FPGA configuration is uploaded from EPCQ and FPGA is booted up, BUT both CPU's are not functioning (i am not sure if it is uploaded or not).

Any idea or advise?

Thanks in advance.

hbs

22 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    The two cpus cannot access the flash at the same time.

    So something must ensure that the first nios completes its boot before the second one starts.

    You could, for instance, arrange for the first cpu to load the code for both cpus, keeping the second cpu in soft-reset until the code (etc) has all been loaded.
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Thank you dsl for your reply

    Can you please en-light me how to put the second cpu in soft-reset.
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Expose the soft reset lines and attach them to a PIO slave (or similar).

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    I managed to use on chip RAM as a boot up for the second CPU.

    The on chip RAM is initialized using a .hex file.

    The first CPU is booting up from EPCQ

    Results:

    Both CPU's are functioning well

    The next step is:

    to change the "Linker Script" in BSP Editor of the second CPU (which booted up from the initialized on chip RAM) as shown in the attached picture

    I also enabled some bits in hal.linker as shown in the attached file (those bits are selected based on http://www.altera.com/literature/hb/nios2/n2sw_nii52015.pdf page 39 )

    Result:

    The second CPU is not booting up any more!

    Any idea?
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    hellow hbs!I want to ask you a few questions.I need tow CPUs in my system,but in my board have only one EPCS flash.in this way,How can I make two CPU start(start after POWER ON RESET POR)?I know hbs may be sucessful;

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    我希望两个cpu都能够上电复位。按照你所说的一个在epcq中，另一个在ram中，但是我怎么弄都没办法让两个cpu上电复位。希望你能够给我些帮助，谢谢

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    如果你能够写一个教程给我，我将万分感激你。我的邮箱地址：[email protected];静候你的回复

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Actually, I did not find a solution for this issue. Altera provided a document for advanced booting

    http://www.google.de/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&cad=rja&uact=8&ved=0cciqfjaa&url=http%3a%2f%2fwww.altera.com%2fliterature%2fan%2fan458.pdf&ei=wgdsu5z0hsjnygo5yogqcw&usg=afqjcnhanm83b3x0wijnzg_ktbqwecojow&sig2=2wdsw_580gm8hp5czcxjoa&bvm=bv.71778758,d.bgq

    However I found that EPCS is not supported in thier advanced boot example.

    In principle, one CPU should hold the second CPU in Reset mode till the first CPU is programmed

    then the first CPU can release the reset pin of the second CPU to let it boot up

    what is not achieved is writing the hex file on a specific address in EPCS and let the second CPU boot from it
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    This "hex file on a specific address " is refers to the base address of memory?