Forum Discussion
Altera_Forum
Honored Contributor
14 years agoTuhran
The phy-addr is determined by which phy you are using. For the Tarasic DE-4 this is hardwired and mapped as follows (see the schematic): Ethernet 0 is phy-addr 0 Ethernet 1 is phy-addr 1 Ethernet 2 is phy-addr 2 Ethernet 3 is phy-addr 3 If you don't specify a phy-addr I think the driver will go search all 32 addresses for attached phys. When I created my CPU design, I used the terasic update portal example to get the ALTERA-TSE settings and connections. This uses the SGMII PCS core variation. Also, the DE4 has the phys connected to the MAC using SGMII. Currently the altera tse driver has the phy interface mode hardcoded, so a little change to the source is required: go to linux-2.6\drivers\net\altera_tse.c In init_phy changeiface = PHY_INTERFACE_MODE_RGMIIto iface = PHY_INTERFACE_MODE_SGMIIalso, the PCS variation of the core uses MDIO space 0 for PCS functions, so you must use MDIO space 1 instead to access the phy registers modify altera_tse_mdio_read (note the 1 instead of the 0)
/* set MDIO address */
writel(mii_id, &mac_dev->mdio_phy1_addr);
mdio_regs = (unsigned int *) &mac_dev->mdio_phy1;
and modify altera_tse_mdio_write in the same way
/* set MDIO address */
writel(mii_id, &mac_dev->mdio_phy1_addr);
mdio_regs = (unsigned int *) &mac_dev->mdio_phy1;
One last important thing of course is that you must have the marvell phy drivers selected in your kernel configuration Cheers Antonie