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Honored ContributorTSE (Triple Speed Ethernet) MAC on uClinux with MMU
Hello all,
I am having some difficulties with the TSE MAC in uClinux with MMU. I am working on Terasic DE4 board, with "unstable-nios2mmu" in linux-2.6 and "trunk" in uClinux-dist. All folders are updated with the update script. I am able to boot the uclinux correctly with my base system, having a ddr2 controller. My next step is to add the tse mac, sgdma-tx, sgdma-rx and descriptor memory for networking. In uClinux configuration (#make menuconfig), I check the Marvell Phy Support and TSE Drivers (SLS). The uClinux compiles and boots, however when I check the networking devices (#ifconfig), the only device is lo; there is no eth0 device. I made no changes on arch/nios2/include/asm/nios.h. Do I need to define a new variable? What if I have multiple TSE instances, then? I don't blame it on my sopc system, at the moment, but more on the configuration I have in uClinux. Any ideas will be appreciated. Kind Regards, Turhan16 Replies
Altera_Forumwhen it starts run on linux
ifconfig eth0 "ip, f.e 192.168.0.1" up you may need to define a mac adress also- Altera_Forum
Thanks Aprado for your response, however eth0 cannot be configured since it is not on the ifconfig list.
When I try to set the Mac address or the IP address# ifconfig eth0 192.168.0.1 up , the response is: ifconfig: SIOCSIFADDR: No such device All the best, Turhan - Altera_Forum
Are you using the device tree method as specified at http://www.alterawiki.com/wiki/devicetree? For now you will need to manually add two properties to the TSE MAC entry in the dts file, so the driver is able to find the PHY. The final entry should look something like this (values may vary depending on your SOPC design):
tse_mac: ethernet@0x8002400 { compatible = "ALTR,tse-9.1","ALTR,tse-1.0"; reg = < 0x8002400 0x400 0x8100000 0x40 0x8200000 0x40 0x4840000 0x2000>; interrupt-parent = < &cpu_0 >; interrupts = < 4 5 >; ALTR,rx-fifo-depth = <1024>; //embeddedsw.CMacro.RECEIVE_FIFO_DEPTH type NUMBER ALTR,tx-fifo-depth = <1024>; //embeddedsw.CMacro.TRANSMIT_FIFO_DEPTH type NUMBER address-bits = <48>; max-frame-size = <1518>; local-mac-address = ; ALTR,mii-id = <0>; // manually added ALTR,phy-addr = <2>; // manually added }; //end ethernet (tse_mac) - Altera_Forum
I cannot thank you enough Tobias. I see now why the devices were not recognized before.
Yes, I use the devicetree method. Could you please explain how do I obtain the values for mii-id and phy addr? The only value with a similar name in SOPC is the PHY ID in SGMII options for the TSE component. I can see that this would work with multiple TSEs and PHYs. How would this affect the mii-id and phy-addr values? Thank you very much, Regards, Turhan - Altera_Forum
On (http://comments.gmane.org/gmane.linux.uclinux.nios2.devel/10), in your discussion with Walter, you have stated that phy-addr is optional. When I tried to use mii-id only, the linux boots and I have the eth0 recognized.
When I run# ifconfig eth0 hw ether 00:11:22:33:44:55 the mac address is set without problems. Then I run# ifconfig eth0 10.0.1.37 skb_over_panic: text:d016ef48 len:65533 put:65533 head:df36e800 data:df36e822 tail:0xdf37e81f end:0xdf36ee20 dev:eth0 BUG: failure at /home/user/Desktop/linuxonAltera/nios2-linux/linux-2.6/net/core/skbuff.c:128/skb_over_panic()! Kernel panic - not syncing: BUG! Is this because I don't have phy-addr variable in dts, or caused by another problem? Have you ever seen such an error before? - Altera_Forum
Tuhran
The phy-addr is determined by which phy you are using. For the Tarasic DE-4 this is hardwired and mapped as follows (see the schematic): Ethernet 0 is phy-addr 0 Ethernet 1 is phy-addr 1 Ethernet 2 is phy-addr 2 Ethernet 3 is phy-addr 3 If you don't specify a phy-addr I think the driver will go search all 32 addresses for attached phys. When I created my CPU design, I used the terasic update portal example to get the ALTERA-TSE settings and connections. This uses the SGMII PCS core variation. Also, the DE4 has the phys connected to the MAC using SGMII. Currently the altera tse driver has the phy interface mode hardcoded, so a little change to the source is required: go to linux-2.6\drivers\net\altera_tse.c In init_phy change
toiface = PHY_INTERFACE_MODE_RGMII
also, the PCS variation of the core uses MDIO space 0 for PCS functions, so you must use MDIO space 1 instead to access the phy registers modify altera_tse_mdio_read (note the 1 instead of the 0)iface = PHY_INTERFACE_MODE_SGMII
and modify altera_tse_mdio_write in the same way/* set MDIO address */ writel(mii_id, &mac_dev->mdio_phy1_addr); mdio_regs = (unsigned int *) &mac_dev->mdio_phy1;
One last important thing of course is that you must have the marvell phy drivers selected in your kernel configuration Cheers Antonie/* set MDIO address */ writel(mii_id, &mac_dev->mdio_phy1_addr); mdio_regs = (unsigned int *) &mac_dev->mdio_phy1; - Altera_Forum
I wouldn't be able to find out about these myself. Thank you so much. Now, as the linux boots, the phy is listed. Which means I am one step closer.
However, when I# ifconfig eth0 10.0.1.37, I still get the kernel panic message in my previous post. I suspect it might be caused by the descriptor memory size in my system. Do you also have a separate memory for descriptor mem, or do you use ddr2 for that? Also, what is the size of your descriptor memory, if it is separate? Thanks again, Turhan - Altera_Forum
Currently my design actually has the descriptor memory located either in onchip memory or ddr2, just like the cyclone III evkit reference design for uClinux with MMU. I think that design is available somewhere on the wiki. The only reason to also have the option of using ddr2 is because u-boot currently only uses ddr2 for the descriptor memory but it is not difficult to make u-boot also use the onchip mem for descriptor use too(i think). I have had the design where only an onchip memory of size 8192 bytes is used for descriptor mem and that seemed to work fine in uClinux.
- Altera_Forum
As already pointed out by tones.rsa, the phy-id is optional. If not specified, the driver will autodetect. What is needed though is the correct mii-id. This one is specific to the board hardware you're using.
Currently you'll need to use a distinguished descriptor memory, otherwise the driver won't work. There once was the option to put the descriptor memory into system memory (DDR or whatever) but that went away when device tree support was merged. We'll need to update the altera_tse driver to be able to do this again. Meanwhile I suggest you'd use a separate descriptor memory if possible. - Altera_Forum
It seems the kernel panic error was my mistake.
After doing the following changes: 1) change descriptor memory size from 2048 to 8192 bytes 2) set the clock domain for each component to 50Hz (no pll output), except ddr2. The ethernet ports are finally working. Cannot thank you enough Tobias and Antonie. Turhan
