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Altera_Forum
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14 years ago

TSE on Cyclone III DSP Deveolpment KIT with uClinux

Hi guys, I have a working project on a Stratix II development board and i have to move it on a cyclone III. I built the new system starting from nios2_linux_3c120_125mhz project, by removing so...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

I'm quite sure. I started from a working project and i made only a few changes (nothing involving TSE or DMA) to adapt it to my requirements. After synthesis I have no error or warning related to timing.

I think there's a problem in the init phase. I tried to execute the superloop example on this design (which is similar to the original ones) and it works, so I'm thinking there's a problem in uClinux driver.