Hi Leon,
I presume you are using signal_tap to probe on RGMII interface. I dig further and found out this is not possible due to this is hard circuitry path in silicon where signal probing is not possible. Refer to KDB link below.
TSE MAC won’t analyze or process 3th or 4th layer info as those are info required by upper layer analysis only. If you refer to AN647, Ethernet packet generator is just generating PRBS data pattern to TSE MAC only.
I suspect below are the 3 reasons causing TSE MAC loopback to fail on your hardware board assuming clock and reset are fine as per your feedback earlier.
- Design timing closure issue
- I forgot to ask you what data rate/speed that you test on hardware ?
- If 10M/100M is working but 1G is failing then it could be due to design timing closure issue as 1G design timing closure is tighter
- TSE IP register is not configured or initialized correctly
- I am not sure how you configure the register in hardware, TCL script or NIOS ?
- Anyway, you can cross check it with AN647 reference design TCL script
- Ethernet data packet is not sent correctly to TSE MAC
- You mentioned simulation is working. So, byright you can monitor the data transaction on ff_tx_* interface and compare the result between sim waveform vs hardware signal_tap
- Again, pls try out AN647 reference design as well
Thanks.
Regards,
dlim
New Contributor
Regular Contributor
