Forum Discussion
Hi dlim,
I am using my own board for hardware testing. I used the board for other projects and I am sure the reset and clock signals works fine.
Thank you for your reference design provided I will check with that.
One concern is I checked the modelsim test bench. The data sending to the TSE only has a Ethernet header and then then the data 0x0102030405.... There is no 3 or 4th layer header(IPv4 or UDP/TCP something) for the data. Do you think that's a problem (I am thinking maybe the TSE detects the packet is not a valid IP data, and drops it)?
In my hardware test, the empty signal of the TSE fifo goes low (indicating data received), and then goes high after several clocks. I assume it dropped the packet since it is not a valid one?
Thank you!
Leon