Tri_state_bridge not reading data bits [31..16] from SRAM

I have a custom board based on the Cyclone III FPGA Starter Kit.

We have recently added SRAM using the IS61LP6432A, a 32 bit device.

In SOPC Builder there is a tri-state bridge which connects the SRAM (CY7C1380C Component) and CFI flash to the NIOS processor.

The tri-state bridge component is configured for the address lines being shared.

The CFI Flash is a 16 bit device which shares its address and data lines with the SRAM. The top 16 data bits of the SRAM are not shared.

In the top level FPGA design:

SRAM_DATA[31..16] is connected to tri_state_bridge_data[31..16]

FLASH_DATA[15..0] is connected to tri_state_bridge_data[15..0]

FLASH_ADDR[22..0] is connected to tri_state_bridge_address[23..1]

The bottom 16 bits are being handled as expected, but when my NIOS program reads 32 bits from SRAM the top 16 bits are always FFFF.

Strangely, when checking the SRAM signals on a scope the data agrees with what was written into the SRAM by NIOS. :confused: