Transferring data from a HDL to the Nios II processor

Hello,

I have a HDL module which is connected to the Avalon bus as a slave component. The component has a FIFO with a length of 4096 * 32 bits values which the processor should read out perdiodically. The processor should always read from the same address.

According to: http://www.altera.com/literature/tt/tt_nios2_tightly_coupled_memory_tutorial.pdf

I should use the IORD macro to read out the data.

The following questions are bothering me:

1. I haven't quite understood why using a pointer to the device address (e.g. int32_t *module_data = MODULE_BASE) won't work. Why does it work for memory (like DDR RAM attached to the processor) but not for a memory mapped device attached to the Avalon bus?

2. Is it possible to use a DMA controller to do the data transfer (is generally possible, e.g. if I would change the module so that every word has its own address)? Transferring the data using only the IORD macro would probably eat a lot of CPU cycles.

Best regards

Martin