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Altera_Forum
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14 years ago

Transferring data from a HDL to the Nios II processor

Hello, I have a HDL module which is connected to the Avalon bus as a slave component. The component has a FIFO with a length of 4096 * 32 bits values which the processor should read out perdiod...
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Altera_Forum
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12 years ago

Yes I've finished my project but I'm using another solution now. I'm not reading from the same address now but have a memory which is attached to the processor.

So what I have now is the following:

- I only need to read data

- The data is stored in dual port RAM which is attached to the processor

So the signal flow looks like this:

custom component -> RAM -> Avalon bus -> NIOS II

To read data from the RAM the processor cache has to be cleared first so that the processor doesn't use old cached data.

I've attached an example of the interface I'm using now. I've taken this from my project and copied the relevant code so you could use it as a starting point. So probably you have to clean up the code before it synthesizes.