Transferring data from a HDL to the Nios II processor

I haven't look at implementing a master but I think a master interface is probably more difficult to implement than the slave interface. I saw that Altera offers a few templates for implementing master interfaces which I'm going to look at for the next project.

The component internally stores the data in addressable registers and then puts the data into the FIFO. The reason for doing it this way was that new data comes into the component at a steady rate. The Nios II has then to send the data over ethernet. As we are not sure that the processor could fetch and send the data fast enough I chose to use the FIFO. Otherwise it could have happened that the processor read data from different sample times because while the processor would still read the old data, new sample data could be written to the registers.